Multi-digit multiplication is widely used for various applications in recent years, including numerical calculation, chaos arithmetic, primality testing. Systems with high performance and low energy consumption are demanded, especially for image processing and communications with cryptography using chaos. Karatsuba algorithm with computational complexity of O(n^1.58) has been employed in software for multiplication of hundreds to thousands bits, where n stands for bit length of operands. In this paper, hardware design of multi-digit integer multiplication based on Karatsuba algorithm is described and its VLSI realization is evaluated in terms of the cost, performance, and energy consumption. We present two design choices of the Karatsuba hardware: RKM (Recursive Karatsuba Multiplier) and IKM (Iterative Karatsuba Multiplier). We found that RKM has less area cost than WTM (Wallace Tree Multiplier) for bit length larger than 2⁹ with area cost of 30mm². Critical path delay of RKM is always larger than that of WTM. Therefore, we should use WTM as combinational circuits for IKM to have better cost performance. We also found that a version of IKM using 0.18μm process can perform 1024-bit multiplications 30 times faster than software at the area cost of 10.9mm². Energy for the computation by the IKM version was found to be nearly 1/600 of that consumed by general purpose processor which executes the software. The results obtained by this study will help system designers for applications requiring multi-digit multiplication to select design alternatives including ASIC realization.